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| TM UCT UCT D ROD TE P TE PRO E SOL STITU OB SUB -5043 Data SheetIBLE March 2000 HI SS PO IH5043 File Number 3130.3 Dual SPDT CMOS Analog Switch [ /Title (IH504 3) /Subject (Dual SPDT CMOS Analog Switch ) /Autho r () /Keywords (Intersil Corporation, semiconductor, Dual SPDT CMOS Analog Switch ) /Creator () /DOCI NFO pdfmark [ The IH5043 analog switch uses an improved, high voltage CMOS monolithic technology. These devices provide ease of use and performance advantages not previously available from solid state switches. Key performance advantage is TTL compatibility and ultra low power operation. The quiescent current requirement is less than 1mA. Also, the IH5043 guarantees Break-BeforeMake switching, accomplished by extending the tON time (300ns Typ), so that it exceeds tOFF time (200ns Typ). This insures that an ON channel will be turned OFF before an OFF channel can turn ON. The need for external logic required to avoid channel to channel shorting during switching is eliminated. Features * See HI504X for Other Functions * Dual SPDT * Switches Greater than 20VP-P Signals with 15V Supplies * Quiescent Current Less than 1mA * Break-Before-Make Switching tOFF 200ns, tON 300ns (Typ) * TTL, DTL, CMOS, PMOS Compatible Pinout IH5043 (PDIP, SOIC) TOP VIEW D1 NC 1 2 3 4 5 6 7 8 16 S1 15 IN1 14 V13 GND 12 VL 11 V+ 10 IN2 9 S2 Part Number Information PART NUMBER IH5043CPE IH5043CY TEMP. RANGE (oC) 0 to 70 0 to 70 PACKAGE 16 Ld PDIP 16 Ld SOIC PKG. NO. E16.3 M16.15 D3 S3 S4 D4 NC D2 Schematic Diagram FUNCTIONAL DRIVER, TYPICAL DRIVER, GATE (1/2 AS SHOWN) V+ Functional Diagram VL Q3 5K Q4 Q1 2K GND IN VL Q2 S3 400 1K 10K Q6 Q5 400 Q7 Q8 Q11 D3 IN2 S2 S4 Q9 S3 S1 FLOATS Q10 D1 IN1 15 10 4 3 D3 S1 16 12 V+ 11 1 D1 9 8 FLOATS Q12 D2 D4 5 13 GND V14 6 SWITCH STATES SHOWN ARE FOR LOGIC "1" INPUT TRUTH TABLE LOGIC V- SWITCH 1, 2 Off On SWITCH 3, 4 On Off 0 1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000 IH5043 Absolute Maximum Ratings V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <36V V+ to VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V VD to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V VD to VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<22V VL to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <33V VL to VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V Continuous Current (S-D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current S-D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . . 70mA Thermal Information Thermal Resistance (Typical, Note 1) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Maximum Junction Temperature (Plastic Packages) . . . . . . .150oC Maximum Storage Temperature. . . . . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V+ = +15V, V- = -15V, VL = +5V (NOTES 2, 3) PER CHANNEL PARAMETER DYNAMIC CHARACTERISTICS Turn ON Time, tON Turn OFF Time, tOFF Charge Injection, Q OFF Isolation, OIRR Crosstalk, CCRR DIGITAL INPUT CHARACTERISTICS Input Logic Current, IIN(ON) Input Logic Current, IIN(OFF) ANALOG SWITCH CHARACTERISTICS Drain-Source ON Resistance, rDS(ON) Channel-to-Channel rDS(ON) Match, rDS(ON) Minimum Analog Signal Handling Capability, VANALOG Switch OFF Leakage Current, ID(OFF), IS(OFF) Switch ON Leakage Current, ID(ON)+IS(ON) POWER SUPPLY CHARACTERISTICS + Power Supply Quiescent Current, I+ - Power Supply Quiescent Current, I+5V Supply Quiescent Current, IL Ground Quiescent Current, IGND NOTES: VIN = 2.4V VIN = 0.8V TEST CONDITIONS 0 oC 25oC 70oC UNITS RL = 1k, VANALOG = -10V to +10V, See Figure 6 See Figure 7 f = 1MHz, RL = 100, CL 5pF, See Figure 4 One Channel Off; Any Other Channel Switches as per Figure 3 - 1000 500 20 (Typ) 50 (Typ) -50 (Typ) - ns ns mV dB dB 1 1 1 1 10 10 A A IS = 10mA, VANALOG = -10V to +10V 80 - 80 30 (Typ) 10 (Typ) 5 10 130 100 100 V nA nA VANALOG = -10V to +10V VD = VS = -10V to +10V - 10 10 10 10 10 10 10 10 100 100 100 100 A A A A 2. Typical values are for design aid only, not guaranteed and not subject to production testing. 3. Min or Max value unless otherwise specified. 2 IH5043 Test Circuits and Waveforms 100 IS = 1mA VS = 15V 80 rDS(ON) () rDS(ON) () 125oC 60 25oC 40 -55oC 160 IS = 1mA 140 120 100 80 60 40 20 20 0 -10.0 0 -10.0 VS = 12V VS = 15V VS = 10V -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0 VANALOG (V) VANALOG (V) FIGURE 1. rDS(ON) vs ANALOG INPUT VOLTAGE -120 CCRR = 20LOG -100 CROSSTALK (dB) VOUT (mVP-P) 2000mVP-P FIGURE 2. rDS(ON) vs POWER SUPPLY VOLTAGE OFF STATE VOUT 100 -80 -60 -40 ON STATE -20 100 0 1 10 100 1K 10K 100K 1M FREQUENCY (Hz) 2VP-P AT 1MHz 51 FIGURE 3A. CROSSTALK vs FREQUENCY FIGURE 3. CROSSTALK FIGURE 3B. TEST CIRCUIT 120 OIRR = 20LOG 100 OFF ISOLATION (dB) 2000mVP-P VOUT (mVP-P) 2VP-P AT 1MHz 80 51 60 OFF STATE 40 100 20 VOUT 0 1 10 100 1K 10K FREQUENCY (Hz) 100K 1M FIGURE 4A. OFF ISOLATION vs FREQUENCY FIGURE 4. OFF ISOLATION FIGURE 4B. TEST CIRCUIT 3 IH5043 Test Circuits and Waveforms (Continued) 3V 0V 0.1T T 1000 IQUIESCENT (EITHER + OR - SUPPLY) (A) ANALOG INPUT 10V 100 0V LOGIC INPUT 10 10pF VOUT 1k 3V LOGIC INPUT 0 1 10 100 1K 10K 100K LOGIC FREQUENCY AT 10% DUTY CYCLE (Hz) FIGURE 5. SUPPLY CURRENT vs LOGIC FREQUENCY FIGURE 6. tON AND tOFF TEST CIRCUIT 45 40 35 QINJECT (mVP-P) 30 25 20 15 10 0 -10.0 0V LOGIC INPUT 10nF VOUT 3V ANALOG INPUT -7.5 -5.0 -2.5 0 2.5 VANALOG (V) 5.0 7.5 10.0 FIGURE 7A. CHARGE INJECTION vs ANALOG INPUT VOLTAGE FIGURE 7. CHARGE INJECTION FIGURE 7B. TEST CIRCUIT 4 IH5043 Typical Applications +15V 2 2 ANALOG INPUT 3 7 CA741 4 -15V 6 1 2 3 4 5 6 7 8 IH5043 16 15 14 13 12 11 10 9 +3V = SAMPLE MODE 0V = HOLD MODE +5V +15V LOGIC INPUT -15V 51 3 CA5420 4 -15V 10,000pF POLYSTYRENE +15V 7 6 OUTPUT FIGURE 8. IMPROVED SAMPLE AND HOLD 1 2 3 4 -VANALOG 16 15 14 13 12 11 10 9 IH5043 +VANALOG T2L LOGIC STROBE -15V EXAMPLE: If -VANALOG = -10VDC and +VANALOG = +10VDC , then Ladder Legs are switched between 10VDC , depending upon state of Logic Strobe. 5 6 7 8 +5V +15V T2L LOGIC STROBE +VANALOG 2R R ETC. R 2R R ETC. 0V = HOLD MODE FIGURE 9. USING THE CMOS SWITCH TO DRIVE AN R/2R LADDER NETWORK (2 LEGS) 5 IH5043 Typical Applications (Continued) 100k HI PASS OUTPUT 100k 10,000pF C CA3440 + 3M 100k 680k R 68k R BANDPASS OUTPUT 10,000pF C CA3440 + 3M LO PASS OUTPUT SIGNAL INPUT 100k CA3440 + 3M 100k 1k 68k R Constant gain, constant Q, variable frequency filter which provides simultaneous Lowpass, Bandpass, and Highpass outputs. With the component values shown, center frequency will be 235Hz and 23.5Hz for high and low logic inputs respectively, Q = 100, and Gain = 100. 1 f N = Center Frequency = ----------------2 RC 680k R IH5043 3V 0V LOGIC STROBE FIGURE 10. DIGITALLY TUNED LOW POWER ACTIVE FILTER 10k +15V REXT (1k TO 20k) IN T2L LOGIC LOGIC INPUT VL 1N914 +15V V+ 20k 15V TTL GATE 15V V+ 5V 0V V- -15V VCMOS GATE V+ 20k VVL VDD 10k V+ GND V+ IN GND FIGURE 11. INTERFACING WITH TTL OPEN COLLECTOR LOGIC (TYP EXAMPLE FOR +15V CASE SHOWN) FIGURE 12. INTERFACING WITH CMOS LOGIC +5V 5k GND IN T2L LOGIC +5V VL V+ +15V OR +VCC (VI TERMINAL) 5V TTL GATE 10 FIGURE 13. TTL LOGIC INTERFACE 6 IH5043 Die Characteristics DIE DIMENSIONS: 1778m x 1905m METALLIZATION: Type: Al Thickness: 10kA 1kA PASSIVATION: Type: PSG/Nitride PSG Thickness: 7kA 1.4kA Nitride Thickness: 8kA 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2 Metallization Mask Layout IH5043 D3 D1 S1 IN1 S3 V- GND VL S4 V+ (SUBSTRATE) D4 D2 S2 IN2 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 7 |
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